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| !" #$% &''()# 8/30/01; v.0.9.5 %% p. 1 of 29 $ ? organization: 2m8 / 1m16 sector architecture - one 16k; two 8k; one 32k; and thirty-one 64k byte sectors - one 8k; two 4k; one 16k; and thirty-one 32k word sectors - boot code sector architecture?t (top) or b (bottom) - erase any combination of sectors or full chip single 2.7-3.6v power supply for read/write operations sector protection high speed 70/80/90/120 ns address access time automated on-chip programming algorithm - automatically programs/verifies data at specified address automated on-chip erase algorithm - automatically preprograms/erases chip or specified sectors hardware reset pin - resets internal state machine to read mode low power consumption - 200 na typical automatic sleep mode current - 200 na typical standby current - 10 ma typical read current jedec standard software, packages and pinouts - 48-pin tsop - 44-pin so (availability tbd) cfi (common flash interface) compliant detection of program/erase cycle completion -dq7 data polling - dq6 toggle bit -ry/by output erase suspend/resume - supports reading data from or programming data to a sector not being erased low v cc write lock-out below 1.5v 10 year data retention at 150c 100,000 write/erase cycle endurance *%+ x decoder v cc v ss cell matrix y decoder y gating data latch chip enable address latch input/output buffers sector protect/ command register program/erase control v cc detector erase voltage generator program voltage generator timer a0?a19 ce oe stb stb output enable logic ry/ by we reset dq0?dq15 (a-1) switches erase voltage byte % 29lv160-70 29lv160-80 29lv160-90 29lv160-120 unit maximum access time t aa 70 80 90 120 ns maximum chip enable access time t ce 70 80 90 120 ns maximum output enable access time t oe 30 30 35 50 ns ( 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a14 a15 a16 byte v ss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v cc a6 a5 a4 a3 a2 a1 a0 ce v ss oe dq0 dq8 dq1 dq9 dq2 dq10 44-pin so 21 22 dq3 dq11 a10 a11 a12 a13 2 a18 3 a17 4 a7 1 reset 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 43 42 41 44 a19 a8 a9 we a8 a9 a10 a11 a12 a13 a14 a15 a16 byte v ss dq15/a-1 dq7 dq14 a19 nc we reset nc nc ry/ by a18 dq2 dq10 dq3 dq11 v cc dq4 dq12 dq5 dq6 dq13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 48 47 46 45 44 43 42 41 40 39 38 37 36 35 15 16 34 33 48-pin tsop a17 a7 a6 a5 a4 a3 a2 a1 a0 ce v ss oe dq0 dq8 dq1 dq9 17 18 19 20 21 22 32 31 30 29 28 27 23 24 26 25 8/30/01; v.0.9.5 %% p. 2 of 29 the AS29LV160 is a 16 megabit, 3.0 volt flash memory organized as 2 megabyte of 8 bits/1 megabyte of 16 bits each. for flexible erase and program capability, the 8 megabits of data is divided into thirty-five sectors: one 16k, two 8k, one 32k, an d thirty-one 64k byte sectors; or one 8k, two 4k, one 16k, and thirty-one 32k word sectors. the 8 data appears on dq0?dq7; the 16 data appears on dq0?dq15. the AS29LV160 is offered in jedec standard 48-pin tsop, 48-pin bga, and 44-pin so (availability tbd) packages. this device is designed to be programmed and erased in-system with a single 3.0v v cc supply. the device can also be reprogrammed in standard eprom programmers. the AS29LV160 offers access times of 70/80/90/120 ns, allowing 0-wait state operation of high speed microprocessors. to eliminate bus contention the device has separate chip enable (ce ), write enable (we ), and output enable (oe ) controls. word mode (16 output) is selected by byte = high. byte mode (8 output) is selected by byte = low. the AS29LV160 is fully compatible with the jedec single power supply flash standard. write commands are sent to the command register using standard microprocessor write timings. an internal state-machine uses register contents to control the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. read data from the device occurs in the same manner as other flash or eprom devices. use the program command sequence to invoke the automated on-chip programming algorithm that automatically times the program pulse widths and verifies proper cell margin. use the erase command sequence to invoke the automated on-chip erase algorithm that preprograms the sector (if it is not already programmed before executing the erase operation), times the erase pulse widths, and verifies proper cell margin. boot sector architecture enables the system to boot from either the top (AS29LV160t) or the bottom (AS29LV160b) sector. sector erase architecture allows specified sectors of memory to be erased and reprogrammed without altering data in other sectors. a sector typically erases and verifies within 1.0 seconds. hardware sector protection disables both program and erase operations in all, or any combination of, the nineteen sectors. the device provides true background erase with erase suspend, which puts erase operations on hold to either read data from, or program data to, a sector that is not being erased. the chip e rase command will automatically erase all unprotected sectors. a factory shipped AS29LV160 is fully erased (all bits = 1). the programming operation sets bits to 0. data is programmed into the array one byte at a time in any sequence and across sector boundaries. a sector must be erased to change bits from 0 to 1. erase returns all bytes in a sector to the erased state (all bits = 1). each sector is erased individually with no effect on ot her sectors. the device features single 3.0v power supply operation for read, write, and erase functions. internally generated and regulated voltages are provided for the program and erase operations. a low v cc detector automatically inhibits write operations during power transtitions. the ry/by pin, data polling of dq7, or toggle bit (dq6) may be used to detect end of program or erase operations. the device automatically resets to the read mode after program/erase operations are completed. dq2 indicates which sectors are being erased. the AS29LV160 resists accidental erasure or spurious programming signals resulting from power transitions. control register architecture permits alteration of memory contents only after successful completion of specific command sequences. during power up, the device is set to read mode with all program/erase commands disabled when v cc is less than v lko (lockout voltage). the command registers are not affected by noise pulses of less than 5 ns on oe , ce, or we . to initiate write commands, ce and we must be logical zero and oe a logical 1. when the device?s hardware reset pin is driven low, any program/erase operation in progress is terminated and the internal state machine is reset to read mode. if the reset pin is tied to the system reset circuitry and a system reset occurs during an automated on-chip program/erase algorithm, data in address locations being operated on may become corrupted and requires rewriting. resetting the device enables the system?s microprocessor to read boot-up firmware from the flash memory. the AS29LV160 uses fowler-nordheim tunnelling to electrically erase all bits within a sector simultaneously. bytes are programmed one at a time using eprom programming mechanism of hot electron injection. 8/30/01; v.0.9.5 %% p. 3 of 29 ! l = low ( # mode ce oe we a0 a1 a6 a9 reset dq id read mfr code llhlllv id hcode id read device code l l h h l l v id hcode read l l h a0a1a6a9 hd out standby hxxxxxxhhigh z output disable lhhxxxxhhigh z write l h l a0 a1 a6 a9 h d in enable sector protect l v id pulse/l l h l v id hx sector unprotect l v id pulse/l l h h v id hx temporary sector unprotect xxxxxxxv id x verify sector protect ? l lhlhlv id hcode verify sector unprotect ? llhlhhv id hcode hardware reset xxxxxxxlhigh z item description id mfr code, device code selected by a9 = v id (9.5v?10.5v), ce = oe = a1 = a6 = l, enabling outputs. when a0 is low (v il ) the output data = 52h, a unique mfr. code for alliance semiconductor flash products. when a0 is high (v ih ), d out represents the device code for the AS29LV160. read mode selected with ce = oe = l, we = h. data is valid in t acc time after addresses are stable, t ce after ce is low and t oe after oe is low. standby selected with ce = h. part is powered down, and i cc reduced to <1.0 a when ce = v cc 0.3v = reset . if activated during an automated on-chip algorithm, the device completes the operation before entering standby. output disable part remains powered up; but outputs tri-stated with oe pulled high. write selected with ce = we = l, oe = h. accomplish all flash erasure and programming through the command register. contents of command register serve as inputs to the internal state machine. address latching occurs on the falling edge of we or ce , whichever occurs later. data latching occurs on the rising edge we or ce , whichever occurs first. filters on we prevent spurious noise events from appearing as write commands. enable sector protect hardware protection circuitry implemented with external programming equipment causes the device to disable program and erase operations for specified sectors. for in-system sector protection, refer to sector protect algorithm on page 15. sector unprotect disables sector protection for all sectors using external programming equipment. all sectors must be protected prior to sector unprotection. for in-system sector unprotection, refer to sector unprotect algorithm on page 15. 8/30/01; v.0.9.5 %% p. 4 of 29 $% ver if y s ec t or protect/ unprotect verifies write protection for sector. sectors are protected from program/erase operations on commercial programming equipment. determine if sector protection exists in a system by writing the id read command sequence and reading location xxx02h, where address bits a12?18 select the defined sector addresses. a logical 1 on dq0 indicates a protected sector; a logical 0 indicates an unprotected sector. te m p o r a r y sector unprotect temporarily disables sector protection for in-system data changes to protected sectors. apply +10v to reset to activate temporary sector unprotect mode. during temporary sector unprotect mode, program protected sectors by selecting the appropriate sector address. all protected sectors revert to protected state on removal of +10v from reset . reset resets the interal state machine to read mode. if device is programming or erasing when reset = l, data may be corrupted. deep power down hold reset low to enter deep power down mode ( < 1 a). recovery time to start of first read cycle is 50ns. automatic sleep mode enabled automatically when addresses remain stable for 300ns. typical current draw is 1 a with no current drawn by the external devices from teh output pin. existing data is available to the system during this mode. if an address is changed, automatic sleep mode is disabled and new data is returned within standard access times. sector bottom boot sector architecture (AS29LV160b) top boot sector architecture (AS29LV160t) 8 16 size (kbytes) 8 16 size (kbytes) 0 000000-003fff 00000-01fff 16 000000-00ffff 00000-07fff 64 1 004000-005fff 02000-02fff 8 010000-01ffff 08000-0ffff 64 2 006000-007fff 03000-03fff 8 020000-02ffff 10000-17fff 64 3 008000-00ffff 04000-07fff 32 030000-03ffff 18000-1ffff 64 4 010000-01ffff 08000-0ffff 64 040000-04ffff 20000-27fff 64 5 020000-02ffff 10000-17fff 64 050000-05ffff 28000-2ffff 64 6 030000-03ffff 18000-1ffff 64 060000-06ffff 30000-37fff 64 7 040000-04ffff 20000-27fff 64 070000-07ffff 38000-3ffff 64 8 050000-05ffff 28000-2ffff 64 080000-08ffff 40000-47fff 64 9 060000-06ffff 30000-37fff 64 090000-09ffff 48000-4ffff 64 10 070000-07ffff 38000-3ffff 64 0a0000-0affff 50000-57fff 64 11 080000-08ffff 40000-47fff 64 0b0000-0bffff 58000-5ffff 64 12 090000-09ffff 48000-4ffff 64 0c0000-0cffff 60000-67fff 64 13 0a0000-0affff 50000-57fff 64 0d0000-0dffff 68000-6ffff 64 14 0b0000-0bffff 58000-5ffff 64 0e0000-0effff 70000-77fff 64 15 0c0000-0cffff 60000-67fff 64 0f0000-0fffff 78000-7ffff 64 16 0d0000-0dffff 68000-6ffff 64 100000-10ffff 80000-87fff 64 17 0e0000-0effff 70000-77fff 64 110000-11ffff 88000-8ffff 64 18 0f0000-0fffff 78000-7ffff 64 120000-12ffff 90000-97fff 64 item description 8/30/01; v.0.9.5 %% p. 5 of 29 in word mode, there are one 8k word, two 4k word, one 16k word, and fifteen 32k word sectors. address range is a19?a-1 if byte = v il ; address range is a19?a0 if byte = v ih . &' % 19 100000-10ffff 80000-87fff 64 130000-13ffff 98000-9ffff 64 20 110000-11ffff 88000-8ffff 64 140000-14ffff a0000-a7fff 64 21 120000-12ffff 90000-97fff 64 150000-15ffff a8000-affff 64 22 130000-13ffff 98000-9ffff 64 160000-16ffff b0000-b7fff 64 23 140000-14ffff a0000-a7fff 64 170000-17ffff b8000-bffff 64 24 150000-15ffff a8000-affff 64 180000-18ffff c0000-c7fff 64 25 160000-16ffff b0000-b7fff 64 190000-19ffff c8000-cffff 64 26 170000-17ffff b8000-bffff 64 1a0000-1affff d0000-d7fff 64 27 180000-18ffff c0000-c7fff 64 1b0000-1bffff d8000-dffff 64 28 190000-19ffff c8000-cffff 64 1c0000-1cffff e0000-e7fff 64 29 1a0000-1affff d0000-d7fff 64 1d0000-1dffff e8000-effff 64 30 1b0000-1bffff d8000-dffff 64 1e0000-1effff f0000-f7fff 64 31 1c0000-1cffff e0000-e7fff 64 1f0000-1f7fff f8000-fbfff 32 32 1d0000-1dffff e8000-effff 64 1f8000-1f9fff fc000-fcfff 8 33 1e0000-1effff f0000-f7fff 64 1fa000-1fbfff fd000-fdfff 8 34 1f0000-1fffff f8000-fffff 64 1fc000-1fffff fe000-fffff 16 sector bottom boot sector architecture (AS29LV160b) top boot sector architecture (AS29LV160t) a19 a18 a17 a16 a15 a14 a13 a12 a19 a18 a17 a16 a15 a14 a13 a12 0 0000000x 00000xxx 1 00000010 00001xxx 2 00000011 00010xxx 3 000001xx 00011xxx 4 00001xxx 00100xxx 5 00010xxx 00101xxx 6 00011xxx 00110xxx 7 00100xxx 00111xxx 8 00101xxx 01000xxx 9 00110xxx 01001xxx 10 00111xxx 01010xxx 11 01000xxx 01011xxx sector bottom boot sector architecture (AS29LV160b) top boot sector architecture (AS29LV160t) 8 16 size (kbytes) 8 16 size (kbytes) 8/30/01; v.0.9.5 %% p. 6 of 29 12 01001xxx 01100xxx 13 01010xxx 01101xxx 14 01011xxx 01110xxx 15 01100xxx 01111xxx 16 01101xxx 10000xxx 17 01110xxx 10001xxx 18 01111xxx 10010xxx 19 10000xxx 10011xxx 20 10001xxx 10100xxx 21 10010xxx 10101xxx 22 10011xxx 10110xxx 23 10100xxx 10111xxx 24 10101xxx 11000xxx 25 10110xxx 11001xxx 26 10111xxx 11010xxx 27 11000xxx 11011xxx 28 11001xxx 11100xxx 29 11010xxx 11101xxx 30 11011xxx 11110xxx 31 11100xxx 111110xx 32 11101xxx 11111100 33 11110xxx 11111101 34 11111xxx 1111111x sector bottom boot sector architecture (AS29LV160b) top boot sector architecture (AS29LV160t) 8/30/01; v.0.9.5 %% p. 7 of 29 # ( )% *+ ' bus write operations 1 key: l =low ( % , # , $ - $ % . / % , 0 ( 0 ( 0 * 2 program 4 555 aa 2aa 55 555 a0 pa pd unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program 2xa0papd unlock bypass reset 2x90xoo chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 block erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 ba 30 erase suspend 1xb0 erase resume 1x30 cfi query 1 x 98 mode a19?a12 a6 a1 a0 code mfr code (alliance semiconductor) x 1 key: l =low ( 8/30/01; v.0.9.5 %% p. 8 of 29 # ( 1)% bus write operations 1 $2 '3 4 5 2 5 4 6 2 % 7 command length 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle address data address data address data address data address data address data read/reset 1xf0 3 aaa aa 555 55 x fo auto select 3 aaa aa 555 55 aaa 90 * 2 # 89 % , 8*+ ' % 9 $ * program 4 aaa aa 555 55 aaa a0 pa pd unlock bypass 3 aaa aa 555 55 aaa 20 unlock bypass program 2xa0papd unlock bypass reset 2x90xoo chip erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 block erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 ba 30 erase suspend 1xb0 erase resume 1x30 cfi query 1 x 98 8/30/01; v.0.9.5 %% p. 9 of 29 # item description reset/read initiate read or reset operations by writing the read/reset command sequence into the command register. this allows the microprocessor to retrieve data from the memory. device remains in read mode until command register contents are altered. device automatically powers up in read/reset state. this feature allows only reads, therefore ensuring no spurious memory content alterations during power up. id read AS29LV160 provides manufacturer and device codes in two ways. external prom programmers typically access the device codes by driving +10v on a9. AS29LV160 also contains an id read command to read the device code with only +3v, since multiplexing +10v on address lines is generally undesirable. initiate device id read by writing the id read command sequence into the command register. follow with a read sequence from address xxx00h to return mfr code. follow id read command sequence with a read sequence from address xxx01h to return device code. to verify write protect status on sectors, read address xxx02h. sector addresses a19?a12 produce a 1 on dq0 for protected sector and a 0 for unprotected sector. exit from id read mode with read/reset command sequence. hardware reset holding reset low for 500 ns resets the device, terminating any operation in progress; data handled in the operation is corrupted. the internal state machine resets 20 s after reset is driven low. ry/by remains low until internal state machine resets. after reset is set high, there is a delay of 50 ns for the device to permit read operations. byte/word programming programming the AS29LV160 is a four bus cycle operation performed on a byte-by-byte or word- by-word basis. two unlock write cycles precede the program setup command and program data write cycle. upon execution of the program command, no additional cpu controls or timings are necessary. addresses are latched on the falling edge of ce or we , whichever is last; data is latched on the rising edge of ce or we , whichever is first. the AS29LV160?s automated on-chip program algorithm provides adequate internally-generated programming pulses and verifies the programmed cell margin. check programming status by sampling data on the ry/by pin, or either the data polling (dq7) or toggle bit (dq6) at the program address location. the programming operation is complete if dq7 returns equivalent data, if dq6 = no toggle, or if ry/by pin = high. the AS29LV160 ignores commands written during programming. a hardware reset occurring during programming may corrupt the data at the programmed location. AS29LV160 allows programming in any sequence, across any sector boundary. changing data from 0 to 1 requires an erase operation. attempting to program data 0 to 1 results in either dq5 = 1 (exceeded programming time limits); reading this data after a read/reset operation returns a 0. when programming time limit is exceeded, dq5 reads high, and dq6 continues to toggle. in this state, a reset command returns the device to read mode. 8/30/01; v.0.9.5 %% p. 10 of 29 unlock bypass command sequence the unlock bypass feature increases the speed at which the system programs bytes or words to the device because it bypasses the first two unlock cycles of the standard program command sequence. to initiate the unlock bypass command sequence, two unlock cycles must be written, then followed by a third cycle which has the unlock bypass command, 20h. the device then begins the unlock bypass mode. in order to program in this mode, a two cycle unlock bypass program sequence is required. the first cycle has the unlock bypass program command, a0h. it is followed by a second cycle which has the program address and data. to program additional data, the same sequence must be followed. the unlock bypass mode has two valid commands, the unlock bypass program command and the unlock bypass reset command. the only way the system can exit the unlock bypass mode is by issuing the unlock bypass reset command sequence. this sequence involves two cycles. the first cycle contains the data, 90h. the second cycle contains the data 00h. addresses are don?t care for both cycles. the device then returns to reading array data. chip erase chip erase requires six bus cycles: two unlock write cycles; a setup command, two additional unlock write cycles; and finally the chip erase command. chip erase does not require logical 0s to be written prior to erasure. when the automated on-chip erase algorithm is invoked with the chip erase command sequence, AS29LV160 automatically programs and verifies the entire memory array for an all-zero pattern prior to erase. the 29lv160 returns to read mode upon completion of chip erase unless dq5 is set high as a result of exceeding time limit. sector erase sector erase requires six bus cycles: two unlock write cycles, a setup command, two additional unlock write cycles, and finally the sector erase command. identify the sector to be erased by addressing any location in the sector. the address is latched on the falling edge of we ; the command, 30h is latched on the rising edge of we . the sector erase operation begins after a sector erase time-out. to erase multiple sectors, write the sector erase command to each of the addresses of sectors to erase after following the six bus cycle operation above. timing between writes of additional sectors must be less than the erase time-out period, or the AS29LV160 ignores the command and erasure begins. during the time-out period any falling edge of we resets the time-out. any command (other than sector erase or erase suspend) during time-out period resets the AS29LV160 to read mode, and the device ignores the sector erase command string. erase such ignored sectors by restarting the sector erase command on the ignored sectors. the entire array need not be written with 0s prior to erasure. AS29LV160 writes 0s to the entire sector prior to electrical erase; writing of 0s affects only selected sectors, leaving non-selected sectors unaffected. AS29LV160 requires no cpu control or timing signals during sector erase operations. automatic sector erase begins after sector erase time-out from the last rising edge of we from the sector erase command stream and ends when the data polling (dq7) is logical 1. data polling address must be performed on addresses that fall within the sectors being erased. AS29LV160 returns to read mode after sector erase unless dq5 is set high by exceeding the time limit. common flash interface in order to achieve long term system compatibility, certain information about the internal configuration of the memory is provided which can be accessed in this mode. according to this information, system software may be configured for both upward and downward compatibility with flash in a similar family. cfi mode can be entered by issuing cfi command either from read or from autoselect mode. the system can read cfi information at the addresses given in the tables below. # item description 8/30/01; v.0.9.5 %% p. 11 of 29 erase suspend erase suspend allows interruption of sector erase operations to read data from or program data to a sector not being erased. erase suspend applies only during sector erase operations, including the time-out period. writing an erase suspend command during sector erase time-out results in immediate termination of the time-out period and suspension of erase operation. AS29LV160 ignores any commands during erase suspend other than read/reset, program or erase resume commands. writing the erase resume command continues erase operations. addresses are don?t care when writing erase suspend or erase resume commands. AS29LV160 takes 0.2?15 s to suspend erase operations after receiving erase suspend command. to determine completion of erase suspend, either check dq6 after selecting an address of a sector not being erased, or poll ry/by . check dq2 in conjunction with dq6 to determine if a sector is being erased. AS29LV160 ignores redundant writes of erase suspend. while in erase-suspend mode, AS29LV160 allows reading data (erase-suspend-read mode) from or programming data (erase-suspend-program mode) to any sector not undergoing sector erase; these operations are treated as standard read or standard programming mode. AS29LV160 defaults to erase-suspend-read mode while an erase operation has been suspended. write the resume command 30h to continue operation of sector erase. AS29LV160 ignores redundant writes of the resume command. AS29LV160 permits multiple suspend/resume operations during sector erase. sector protect when attempting to write to a protected sector, data polling and toggle bit 1 (dq6) are activated for about <1 s. when attempting to erase a protected sector, data polling and toggle bit 1 (dq6) are activated for about <5 s. in both cases, the device returns to read mode without altering the specified sectors. # item description 8/30/01; v.0.9.5 %% p. 12 of 29 & % : " & # ; & # & # ' < '# addresses (word mode) addresses (byte mode) data description 10h 20h 0051h query unique ascii string (qry) 11h 22h 0052h 12h 24h 0059h 13h 26h 0002h primary oem command set 14h 28h 0000h 15h 2ah 0040h address for primary extended table 16h 2ch 0000h 17h 2eh 0000h alternate oem command set (00h = does not exist) 18h 30h 0000h 19h 32h 0000h address for alternate oem extended table (00h = does not exist) 1ah 34h 0000h addresses (word mode) addresses (byte mode) data description 1bh 36h 0027h vccmin.(write/erase), d7-d4:volt, d3-d0: 100 millivolt 1ch 38h 0036h vccmax.(write/erase), d7-d4: volt, d3-d0: 100 millivolt 1dh 3ah 0000h vppmin. voltage (00h = no vpp pin present) 1eh 3ch 0000h vppmax. voltage (00h = no vpp in present) 1fh 3eh 0004h typical timeout per single byte/word write 2 n us 20h 40h 0000h typical timeout for min. size buffer write 2 n us (00h = not supported) 21h 42h 000ah typical timeout per individual block erase 2 n ms 22h 44h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 46h 0005h max. timeout for byte/word write 2 n times typical 24h 48h 0000h max. timeout for buffer write 2 n times typical 25h 4ah 0004h max. timeout per individual block erase 2 n times typical 26h 4ch 0000h max. timeout for full chip erase 2 n times typical (00h = not supported) addresses (word mode) addresses (byte mode) data description 27h 4eh 0015h device size = 2 n byte 28h 50h 0002h flash device interface description 29h 52h 0000h 2ah 54h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2bh 56h 0000h 2ch 58h 0004h number of erase block regions within device 2dh 5ah 0000h erase block region 1 information 2eh 5ch 0000h 2fh 5eh 0040h 30h 60h 0000h 8/30/01; v.0.9.5 %% p. 13 of 29 5 )# +$ ; 31h 62h 0001h erase block region 2 information 32h 64h 0000h 33h 66h 0020h 34h 68h 0000h 35h 6ah 0000h erase block region 3 information 36h 6ch 0000h 37h 6eh 0080h 38h 70h 0000h 39h 72h 001eh erase block region 4 information 3ah 74h 0000h 3bh 76h 0000h 3ch 78h 0001h addresses (word mode) addresses (byte mode) data description 40h 80h 0050h query-unique ascii string (pri) 41h 82h 0052h 42h 84h 0049h 43h 86h 0031h major version number, ascii 44h 88h 0030h minor version number, ascii 45h 8ah 0000h address sensitive unlock, 0 = required, 1 = not required 46h 8ch 0002h erase suspend, 0 = not supported, 1 = to read only, 2 = to read and write 47h 8eh 0001h sector protect, 0 = not supported, x = number of sectors in per group 48h 90h 0001h sector temporary unprotect, 00 = not supported, 01 = supported 49h 92h 0004h sector protect/unprotect scheme 4ah 94h 0000h simultaneous operation, 00 = not supported, 01 = supported 4bh 96h 0000h burst mode type, 00 = not supported , 01 = supported 4ch 98h 0000h page mode type, 00 = not supported, 01 = 4 word page, 02 = 8 word page addresses (word mode) addresses (byte mode) data description 8/30/01; v.0.9.5 %% p. 14 of 29 = dq2 toggles when an erase-suspended sector is read repeatedly. dq6 toggles when any address is read repeatedly. dq2 = 1 if byte address being programmed is read during erase-suspend program mode. ? dq2 toggles when the read address applied points to a sector which is undergoing erase, suspended erase, or a failure to erase. data polling (dq7) only active during automated on-chip algorithms or sector erase time outs. dq7 reflects complement of data last written when read during the automated on-chip program algorithm (0 during erase algorithm); reflects true data when read after completion of an automated on-chip program algorithm (1 after completion of erase agorithm). toggle bit 1 (dq6) active during automated on-chip algorithms or sector erase time outs. dq6 toggles when ce or oe toggles, or an erase resume command is invoked. dq6 is valid after the rising edge of the fourth pulse of we during programming; after the rising edge of the sixth we pulse during chip erase; after the last rising edge of the sector erase we pulse for sector erase. for protected sectors, dq6 toggles for <1 s during program mode writes, and <5 s during erase (if all selected sectors are protected). exceeding time limit (dq5) indicates unsuccessful completion of program/erase operation (dq5 = 1). data polling remains active. if dq5 = 1 during chip erase, all or some sectors are defective; during byte programming or sector erase, the sector is defective (in this case, reset the device and execute a program or erase command sequence to continue working with functional sectors). attempting to program 0 to 1 will set dq5 = 1. sector erase timer (dq3) checks whether sector erase timer window is open. if dq3 = 1, erase is in progress; no commands will be accepted. if dq3 = 0, the device will accept sector erase commands. check dq3 before and after each sector erase command to verify that the command was accepted. toggle bit 2 (dq2) during sector erase, dq2 toggles with oe or ce only during an attempt to read a sector being erased. during chip erase, dq2 toggles with oe or ce for all addresses. if dq5 = 1, dq2 toggles only at sector addresses where failure occurred, and will not toggle at other sector addresses. use dq2 in conjunction with dq6 to determine whether device is in auto erase or erase suspend mode. ready/busy ry/ by indicates whether an automated on-chip algorithm is in progress (ry/by = low) or completed (ry/by = high). the device does not accept program/erase commands when ry/ by = low. ry/by = high when device is in erase suspend mode. ry/by = high when device exceeds time limit, indicating that a program or erase operation has failed. ry/by is an open drain output, enabling multiple ry/by pins to be tied in parallel with a pull up resistor to v cc . status dq7 dq6 dq5 dq3 dq2 ry/by standard mode auto programming dq 7 toggle 0 n/a no toggle 0 program/erase in auto erase 0 toggle 0 1 toggle ? 0 erase suspend mode read erasing sector 1 no toggle 0 n/a toggle 1 read non-erasing sector data data data data data 1 program in erase suspend dq 7 toggle 0 n/a toggle ? 0 exceeded time limits auto programming (byte) dq 7 toggle 1 n/a no toggle 1 program/erase in auto erase 0 toggle 1 n/a toggle ? 1 program in erase suspend (non-erase suspended sector) dq 7 toggle 1 n/a no toggle 1 8/30/01; v.0.9.5 %% p. 15 of 29 start plscnt = 1 reset# = v id wait 1 s first write cycle=60h? temporary sector unprotect mode no set up sector sector protect: address write 60h to sector address with a6=0, a1=1, a0=0 wait 150 s verify sector protect; write 40h to sector address with a6=0, a1=1, a0=0 read from sector address with a6=0, a1=1, a0=0 data=01h? protect sector? plscnt=25? no increment plscnt no device failed yes yes yes no start plscnt = 1 reset# = v id wait 1 s first write cycle=60h? temporary sector unprotect mode no yes all sectors protected? set up first sector unprotect: sector address write 60h to sector address with a6=1, a1=1, a0=0 wait 15 ms verify sector unprotect; write 40h to sector address with a6=1, a1=1, a0=0 read from sector address with a6=1, a1=1, a0=0 data=00h? last sector verified? no yes yes remove v id from reset# write reset command sector unprotect complete remove v id from reset# write reset command sector protect complete plscnt increment plscnt no device failed yes =1000? set up next sector address no protect all sectors: the shaded portion of the sector protct initiated for all unprotected sectors before calling the sector unprotect no yes yes algorithm must be another 8/30/01; v.0.9.5 %% p. 16 of 29 ) ) ? the system software should check the status of dq3 prior to and following each subsequent sector erase command to ensure command completion. the device may not have accepted the command if dq3 is high on second status check. start 555h/aah 2aah/55h 555h/a0h program address/program data program command sequence 16 mode (address/data): write program command sequence (see below) data polling or toggle bit successfully completed last address? programming completed yes increment address no 555h/aah 2aah/55h 555h/80h erase command sequence 555h/aah 2aah/55h sector address/30h erase complete 16 mode (address/data): data polling or toggle bit successfully completed write erase command sequence (see below) 555h/aah 2aah/55h 555h/80h chip erase command sequence 555h/aah 2aah/55h 555h/10h 16 mode (address/data): individual sector/multiple sector sector address/30h sector address/30h optional sector erase commands start 8/30/01; v.0.9.5 %% p. 17 of 29 5 7 % start write unlock bypass command (3 cycles) write unlock bypass program command (2 cycles) data polling or last address? yes increment address no write unlock bypass reset command (2 cycles) programming completed toggle bit successfully completed 555h/aah 2aah/55h 555h/20h unlock bypass command sequence x16 mode (address/data) xxxh/a0h unlock bypass program x16 mode (address/data) command sequence program address/ program data xxxh/90h unlock bypass reset x16 mode (address/data) command sequence xxxh/00h 8/30/01; v.0.9.5 %% p. 18 of 29 ' / ? va = byte address for programming. va = any of the sector addresses within the sector being erased during sector erase. va = va lid address equals any non-protected sector group address during chip erase. ? dq7 rechecked even if dq5 = 1 because dq5 and dq7 may not change simultaneously. read byte (dq0?dq7) address = va ? read byte (dq0?dq7) address = va no done no no ? yes fail yes ? yes done dq7 = data ? dq5 = 1 ? dq7 = data ? ? 8/30/01; v.0.9.5 %% p. 19 of 29 / % ? dq6 rechecked even if dq5 = 1 because dq6 may stop toggling when dq5 changes to 1. read byte (dq0?dq7) address = don?t care read byte (dq0?dq7) address = don?t care no done yes yes yes fail no no done dq6 = toggle ? dq6 = toggle ? ? dq5 = 1 ? 8/30/01; v.0.9.5 %% p. 20 of 29 ' 2 >?@ parameter symbol test conditions min max unit input load current i li v in = v ss to v cc , v cc = v cc max -1 a a9 input load current i lit v cc = v cc max , a9 = 10v 35 a output leakage current i lo v out = v ss to v cc , v cc = v cc max -1 a active current, read @ 5mhz i cc1 ce = v il , oe = v ih -20ma active current, program/erase i cc2 ce = v il , oe = v ih -30ma automatic sleep mode 1 1 automatic sleep mode enables the deep power down mode when addresses are stable for 150 ns. typical sleep mode current is 200 na. i cc3 ce = v il , oe = v ih ; v il = 0.3v, v ih = v cc - 0.3v -5a standby current i sb ce = v cc - 0.3v, reset = v cc - .3v - 5 a deep power down current 3 i pd reset = 0.3v - 5 a input low voltage v il -0.5 0.8 v input high voltage v ih 0.7v cc v cc + 0.3 v output low voltage v ol i ol = 4.0ma, v cc = v cc min -0.45v output high voltage v oh i oh = -2.0 ma, v cc = v cc min 0.85v cc -v low v cc lock out voltage v lko 1.5 - v input hv select voltage v id 911v 8/30/01; v.0.9.5 %% p. 21 of 29 a * ,# jedec symbol std symbol parameter -70 -80 -90 -120 unit min max min max min max min max t avav t rc read cycle time 70 - 80 - 90 - 120 - ns t av q v t acc address to output delay - 70 - 80 - 90 - 120 ns t elqv t ce chip enable to output - 70 - 80 - 90 - 120 ns t glqv t oe output enable to output - 30 - 30 - 35 - 50 ns t oes output enable setup time 0 - 0 - 0 - 0 - ns t ehqz t df chip enable to output high z - 25 - 25 - 30 - 30 ns t ghqz t df output enable to output high z - 25 - 25 - 30 - 30 ns t axqx t oh output hold time from addresses, first occurrence of ce or oe 0-0-0-0-ns t oeh output enable hold time: read 10 - 10 - 10 - 10 - ns output enable hold time: toggle and data polling 10 - 10 - 10 - 10 - ns t phqv t rh reset high to output delay - 50 - 50 - 50 - 50 ns t ready reset pin low to read mode - 10 - 10 - 10 - 10 s t rp reset pulse 500 - 500 - 500 - 500 - ns addresses stable addresses t rc t acc t oe t oeh t ce t oh t df ce oe we outputs high z high z output valid t rh reset t oes 8/30/01; v.0.9.5 %% p. 22 of 29 a , =+ = ,# =+ jedec symbol std symbol parameter -70 -80 -90 -120 unit min max min max min max min max t avav t wc write cycle time 70 - 80 - 90 - 120 - ns t avwl t as address setup time 0 - 0 - 0 - 0 - ns t wlax t ah address hold time 45 - 45 - 45 - 50 - ns t dvwh t ds data setup time 35 - 35 - 45 - 50 - ns t whdx t dh data hold time 0 - 0 - 0 - 0 - ns t ghwl t ghwl read recover time before write 0 - 0 - 0 - 0 - ns t elwl t cs ce setup time 0-0-0-0-ns t wheh t ch ce hold time 0-0-0-0-ns t wlwh t wp write pulse width 35 - 35 - 35 - 50 - ns t whwl t wph write pulse width high 30 - 30 - 30 - 30 - ns addresses ce oe we data t wc t as t ah t ghwl ; t oes t wp t cs t wph t dh t whwh1 or 2 t ds dq 7d out program 555h program address program address 3rd bus cycle t ch data polling a0h data 8/30/01; v.0.9.5 %% p. 23 of 29 a , + = ,# + jedec symbol std symbol parameter -70 -80 -90 -120 unit min max min max min max min max t avav t wc write cycle time 70 - 80 - 90 - 120 - ns t avel t as address setup time 0 - 0 - 0 - 0 - ns t elax t ah address hold time 45 - 45 - 45 - 50 - ns t dve h t ds data setup time 35 - 35 - 45 - 50 - ns t ehdx t dh data hold time 0 - 0 - 0 - 0 - ns t ghel t ghel read recover time before write 0 - 0 - 0 - 0 - ns t wlel t ws we setup time 0 - 0 - 0 - 0 - ns t ehwh t wh we hold time 0 - 0 - 0 - 0 - ns t eleh t cp ce pulse width 35 - 35 - 35 - 50 - ns t ehel t cph ce pulse width high 30 - 30 - 30 - 30 - ns addresses we oe ce data program address 555h program address a0h program dq 7d out t wc t as t ah t cp t cph t dh t ds t whwh1 or 2 data polling data t ghel , t oes 8/30/01; v.0.9.5 %% p. 24 of 29 a / ,# a *++/ *++/ ,# + ,# b jedec symbol std symbol parameter -70/80/90/120 unit min max t vidr v id rise and fall time 500 - ns t rsp reset setup time for temporary sector unprotect 4-s jedec symbol std symbol parameter -70/80/90/120 unit min max t rp reset pulse 500 - ns t rh reset high time before read 50 - ns t ready reset low to read mode -20s reset ce we ry/by 0 or 3v t vidr t vidr 0 or 3v t rsp program/erase command sequence 12v reset ry/by dq t rp t ready t rp t rh valid data valid data status status addresses ce oe we data 555h 2aah 555h 555h 2aah sector address t wc t as t ah t ghwl aah 55h 80h aah 55h 30h 10h for chip erase t wp t cs t wph t dh t ds t wc 8/30/01; v.0.9.5 %% p. 25 of 29 5 a *+ 'cd6ec *cd6c ,# ' / ,# / % ,# jedec symbol std symbol parameter -70/80/90/120 unit min max -t vcs v cc setup time 50 - s -t rb recovery time from ry/by 0- ns -t busy program/erase valid to ry/by delay 90 - ns ce we ry/ b y rising edge of last we signal program/erase operation tri-stated open-drain v cc t vcs t rb t busy ce oe we dq7 t ch t oh t whwh1 or 2 t oe t oeh t ce t df high z input dq7 output dq 7output ce we oe dq6 t oeh t dh t oe toggle toggle no toggle 8/30/01; v.0.9.5 %% p. 26 of 29 =d% # 6c/+ ,# 6c/+ , ,# d jedec symbol std symbol parameter -70/80/90/120 unit min max -t elfl /t elfh ce to byte switching low or high -10 ns -t flqz byte switching low to output high-z -30 ns -t fhqz byte switching high to output active 80 - ns ce oe byte dq0-dq14 dq15/a-1 byte dq0-dq14 dq15/a-1 byte wor d to byte byte to wor d data output data output address input dq15 output data output dq0-dq7 dq0-dq14 dq0-dq7 data output dq0-dq14 address input dq15 output t elfl t elfh t flqz t fhqv ce we byte falling edge of last we signal t set (t as )t hold (t ah ) see erase/program operations table for t as and t ah specifications. reset# ce# oe# * for sector protect, a6=0, a1=1, a0=0. for sector unprotect, a6=1, a1=1, a0=0. v id v ih valid* valid* valid* sa, a6, a1, a0 60h 40h status 60h data sector protect/unprotect 1 s sector protect: 100 s sector unprotect: 10 ms we# verify don?t care don?t care don?t care don?t care don?t care 8/30/01; v.0.9.5 %% p. 27 of 29 / # # + # includes all pins except v cc . test conditions: v cc = 3.0v, one pin at a time. test condition -70, -80 -90, -120 unit output load 1 ttl gate output load capacitance c l (including jig capacitance) 30 100 pf input rise and fall times 5ns input pulse levels 0.0-3.0 v input timing measurement reference levels 1.5 v output timing measurement reference levels 1.5 v parameter limits unit min typical max sector erase and verify-1 time (excludes 00h programming prior to erase) - 1.0 15 sec programming time byte - 10 300 s wo r d - 1 5 3 6 0 s chip programming time - 7.2 27 sec erase/program cycles 1 1 erase/program cycle test is not verified on each shipped unit. -100,000- cycles parameter min max unit input voltage with respect to v ss on a9, oe, and reset pin -1.0 +12.0 v input voltage with respect to v ss on all dq, address, and control pins -0.5 vcc +0.5 v current -100 +100 ma f ? g >f ? ' h@ i@ j k i@ j k 8/30/01; v.0.9.5 %% p. 28 of 29 * % $ stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not im plied. exposure to absolute maximum rating conditions for extended periods may affect reliability. /!5 ! - % /6'. ' parameter symbol min max unit supply voltage v cc +2.7 +3.6 v v ss 00v input voltage v ih 1.9 v cc + 0.3 v v il ?0.5 0.8 v parameter symbol min max unit input voltage (input or dq pin) v in ?0.5 v cc + 0.5 v input voltage (a9 pin, oe , reset )v in ?0.5 +12.5 v power supply voltage v cc -0.5 +4.0 v operating temperature t opr ?55 +125 c storage temperature (plastic) t stg ?65 +150 c short circuit output current i out -150ma symbol parameter test setup typ max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 8 10 pf symbol parameter test setup typ max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 8 10 pf parameter temp.(c) min unit minimum pattern data retention time 150 10 years 125 20 years 8/30/01; v.0.9.5 %% p. 29 of 29 ? copyright alliance semiconductor corporation. all rights reserved. our three-point logo, our name and intelliwatt are tradema rks or registered trademarks of alliance. all other brand and product names may be the trade- marks of their respective companies. alliance reserves the right to make changes to this document and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance?s best data and/or estimates at the time of issuance. alliance reserves the right to change or correct this data at any time, without notice. if the product described herein is under development, significant changes to these specifications are possible. the information in this product data sheet is intended t o be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or liability ar ising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in alliance?s terms and conditions of sale (which are available from alliance). all sales of alliance product s are made exclusively according to alliance?s terms and conditions of sale. the purchase of products from alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any oth er intellectual property rights of alliance or third parties. alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result i n significant injury to the user, and the inclusion of alliance products in such life-supporting sys- tems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against all claims arising fro m such use. e b e hd d 48-pin 1220 min max a ? 1.27 a1 0.05 0.15 a2 0.95 1.05 b0.170.27 c 0.15 nominal d 18.20 18.60 e 0.50 nominal e 11.90 12.10 hd 19.80 20.20 l0.500.70 0 5 c l a1 a a2 48-pin pin 1 pin 48 pin 24 pin 25 5 7 : / 7 -/!5)&. 57 : ! 5 -!. - % /6'. d h e 1234567891011121314 44 43 42 41 40 39 38 37 36 35 34 33 32 31 15 16 30 29 17 18 19 20 28 27 26 25 c l a 1 a 2 e so 0?10 21 24 22 23 e a b jedec mo - 175 aa 44-pin so min (mm) max (mm) a?3.1 a1 0.05 ? a2 2.5 2.9 b0.250.45 c0.09 0.25 d 28.0 28.4 e 12.4 12.8 e 1.27 (typical) he 16.05 (typical) l0.731.3 |
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